Altera's Quartus II Version 3.0 Design Software Delivers Direct Path to ASIC-Level Performance
$2,000 Quartus II Software Supports HardCopy Stratix Devices, Providing the Industry's First Complete FPGA-to-Mask-Programmed Device Design Tool
SAN JOSE, Calif., June 24 /PRNewswire-FirstCall/ -- Altera Corporation , today unveiled version 3.0 of its Quartus(R) II design software, featuring the industry's first design flow for the development of both FPGAs and ASIC-like low-cost mask-programmed devices. With the Quartus II version 3.0 design software, system designers can now directly target HardCopy Stratix(TM) devices so they can predict and verify their devices' performance, which on average is 50 percent faster than equivalent FPGAs. In addition to the HardCopy Stratix device design flow, the Quartus II version 3.0 design software introduces a suite of new features that reduce design cycle times for Altera's CPLDs, FPGAs, and HardCopy devices. In contrast to ASIC design tools, which can cost several hundred thousand dollars, the Quartus II 3.0 development software has a licensing fee of only $2,000.
"Altera's FPGAs offer ASIC-like complexity and density, and have enabled BlueArc to implement a groundbreaking file server architecture with world-leading performance. These advanced FPGAs require correspondingly advanced development tools," said Shmuel Shottan, senior vice president of engineering at BlueArc Corporation. "Altera's Quartus II 3.0 provides the right features to enable system designers to achieve ASIC development flow efficiency while benefiting from the flexibility of FPGAs. The Tcl interface which allows designers to integrate and control memory functions via scripting, unavailable in competitive programmable logic tools, is especially welcome."
This new version of the software now delivers the design performance metrics for HardCopy Stratix devices as early in the development process as for FPGAs. Designers can now assess their HardCopy Stratix design's fMAX performance, power consumption, logic cell placement, and I/O assignment -- all before implementing the design into the final mask-programmed device. This upfront capability is essential for starting system-level board design.
"A seamless design flow from an FPGA to mask-programmed device is a significant industry first because it reduces the risk and time involved in developing lower-cost devices for volume applications," said analyst Cary Snyder of Forward Concepts. "By having the design flow for HardCopy Stratix devices incorporated into Quartus II design software, Altera is taking an important step forward in providing designers with a low-cost design tool that gives them complete control over both Stratix and HardCopy versions of their designs. This more efficiently meets the needs of design teams who are under increasing pressure to cut total design costs."
Quartus II Version 3.0 Design Software Features and Benefits
Quartus II version 3.0 design software slashes FPGA design and verification times by introducing a suite of new features and enhancements to address common design flow bottlenecks.
-- Enhanced I/O Pin Assignment and Validation - This feature allows I/O
assignment and validation to be performed before top-level entities or
modules are available. The capability allows printed circuit board
(PCB) layout to begin earlier in the design process.
-- Chip Editor - Quartus II users can now make small manual design changes
directly to an optimized design in minutes without conducting a design
compilation or losing timing closure.
-- Incremental Compilation - This new feature limits logic placement
changes during the place and route process to those introduced by
incremental changes to any design source files. Additionally, using
this feature decreases compilation run times by 40 percent on average.
Placement, and hence timing, in remaining portions of the design are
not affected.
-- System-Level Design Improvements - SOPC Builder, now included with the
Quartus II design software, automates adding, parameterizing, and
linking intellectual property (IP) cores, including embedded
processors, co-processors, peripherals, memories, and user-defined
logic. This release also includes the first SOPC Builder support for
the Red Hat Linux operating system.
-- Block-Based Design Improvements - The LogicLock(TM) block-based design
methodology allows Quartus II users to design and implement design
modules independently and maintain performance while integrating
modules into a top-level project. With the Quartus II version 3.0
design software, system architects now have the capability to lock down
routing as well as logic placement when integrating modules.
-- Command Line & Tcl Scripting Interface - This new command line
interface allows designers to run the Quartus II design software from
make files or Tcl scripts utilizing a new simplified programming
syntax. An added benefit from the new command line interface is faster
file loading and execution in distributed networked environments.
-- Design Space Explorer - This new feature automates the design
optimization process and increases average push-button design
performance on average 20 percent by automatically applying
combinations of advanced compiler optimization settings.
-- ModelSim-Altera Software Improvements - Quartus II users can now
perform behavioral and timing simulation up to 20 percent faster using
the new ModelSim(R)-Altera version 5.7c software. This software is
included with Altera's software subscription.
"System designers now have a virtual desktop foundry, equipping them with the necessary tools to target their designs for PLDs or a low-cost ASIC alternative. The choice is theirs," said Tim Southgate, vice president, of software tools marketing at Altera. "This is the first time that ASIC designers have access to a virtually risk-free, very low-cost, easy-to-use design flow, where designs can be functionally tested in-system using a pin- and resource-compatible FPGA."
Pricing and Availability
Quartus II version 3.0 design software is now shipping to all customers with an active software subscription. Altera's software subscription program simplifies the process of obtaining Altera design software by consolidating all software products and maintenance charges into one annual subscription payment. The annual subscription for the Altera design software is $2,000 for a node-locked PC license, which includes full-featured Quartus II design software, SOPC Builder system generation and integration software, OEM simulation tools from Model Technology, and 12 months of software upgrades. The Quartus II design software supports major operating systems, including Windows XP, Windows 2000, Windows NT, Sun Solaris, Red Hat Linux, and HP-UX. New or existing customers may obtain a software subscription on-line on the Altera web site, http://www.altera.com/, or from Altera distributors worldwide. Free Quartus II Web Edition software is available from the Altera web site.
About HardCopy Stratix Devices
Altera's HardCopy Stratix devices are the industry's only low-cost mask-programmed devices with ASIC-level performance, price, and features that customers can take to production virtually risk-free. This unique ASIC-alternative is directly accessible for design through Altera's Quartus II version 3.0 design software. The HardCopy Stratix devices maintain the same features as the successful Stratix FPGAs and on average a 50 percent performance increase and up to a 40 percent decrease in power consumption over the equivalent Stratix FPGAs. Altera's HardCopy Stratix devices are ideal for high-performance, high-volume applications in the networking, wireless communication, high- end consumer electronics, industrial, test, and medical markets. For more information about the HardCopy Stratix devices, please visit http://www.altera.com/hardcopystratix
About Altera
Celebrating its 20th anniversary this year, Altera Corporation is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at http://www.altera.com/.
NOTE: Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders.
Editor Contact:
Ami Dorrell
Altera Corporation
408-544-6397
newsroom@altera.com
CONTACT: Ami Dorrell of Altera Corporation, +1-408-544-6397, or
newsroom@altera.com
Web site: http://www.altera.com/
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